The invention relates to the field of fabricating semiconductor devices and other electronic devices, and more particularly to method of filling trenches or via holes with a uniform layer of semiconductive or conductive material.
Two features that are repeatedly formed during semiconductor processing are trenches and via holes in order to fabricate interconnects or different types of cells in a device. The process of fabricating these features typically involves patterning a photoresist layer and then using the photoresist as a mask while the pattern is etched into one or more underlying layers. One characteristic of trenches, especially those in a deep trench (DT) pattern, is a high aspect ratio in which the height of the trench is several times the width of the opening. This relationship requires low edge roughness and high etch resistance in the photoresist so that smooth sidewalls can be formed in the etched trench pattern. Furthermore, the etch should be anisotropic and be able to generate vertical profiles in the etched pattern.
Another challenging aspect of semiconductor processing is filling trenches and via holes with a uniform layer of material that is free of voids and seams. This process is becoming increasingly difficult as the size of trench and via openings shrinks in order to keep pace with a constant demand for higher performance in semiconductor devices. When interconnects are filled with a conductive material, a metal or metal alloy involving copper, aluminum, or tungsten is generally deposited although metal suicides are also good conductors. Deposition is accomplished by electroplating, evaporating or sputtering methods.
DT cells are commonly filled with a material like silicon. Seams can easily form in the deposited material inside the trench. As a result, the manufacturing process will be more expensive because the defective substrates will have to be reworked or scrapped. When the defects go undetected, then there will be a loss of performance in the final device. Therefore, it is desirable to employ a reliable method of filling holes and trenches that does not form seams and can be implemented in a cost effective manner.
A vapor-liquid-solid (VLS) mechanism of single crystal growth is proposed by R. Wagner and W. Ellis in Applied Phys. Letters, Vol. 4, No. 5, p. 89 (1964). This paper reports the growth of a 0.2 micron single crystal or whisker of silicon on a Si substrate by using a Au particle as a seed material and a SiCl4 vapor as a silicon source that is reduced by H2. The authors postulate that a liquid alloy droplet is formed on the Au impurity. Vapor deposition occurs on the droplet and the liquid becomes supersaturated with silicon. Silicon precipitation causes the whisker to grow and the alloy droplet is believed to xe2x80x9cridexe2x80x9d on top of the whisker as it grows.
Since then the VLS mechanism has been applied for industrial uses. In U.S. Pat. No. 5,207,263, a VLS silicon carbide whisker is combined with a metal in a squeeze casting process to form a reinforced metal composite. The SiC whisker is characterized by a high length/width aspect ratio. Silica, alumina, carbon, and boron are mentioned as other sources of VLS growth.
A silicon nitride nanowhisker is described for use in ceramics applications in U.S. Pat. 5,814,290. A nanowhisker with a diameter of from 30 to 200 nm and a length of greater than a millimeter can be formed with straight needle-like morphology by reacting gaseous SiO and nitrogen at elevated temperature and pressure. The nanowhiskers are grown in the presence of carbon nanotubes in a temperature range of from 1200xc2x0 C. to 1400xc2x0 C.
U.S. Pat. No. 5,362,972 describes the formation of a semiconductor whisker channel by organometallic vapor phase (MOCVD) epitaxy. An n-type InAs whisker is grown on a GaAs or InP substrate and becomes a gate in a field effect transistor. In another embodiment, an InGaAs gate with a gate length of 50 nm is formed. The whisker growth is controlled by the supply rate of arsine which is thermally decomposed at about 400xc2x0 C. during the reaction with implanted gallium or indium ions. A typical growth time is about 200 seconds. These whiskers provide higher electron mobility than gates formed by conventional methods.
An objective of the present invention is to provide a method for filling trenches and via holes without forming seams that will improve reliability of the final device.
A further objective of the present invention is to provide a method of filling trenches that can be readily implemented in manufacturing using existing tools.
These objectives are achieved by employing a VLS process for filling a trench or via hole. In one embodiment, a thin film of silicon that is optionally doped with arsenic is grown on the walls of a trench. A seed material such as Au, Ni, Co or an alloy of one of the aforesaid metals is deposited on the trench walls by electroless plating. A heat treatment is then used to reflow the seed material to a liquid state at the bottom of the trench. A silicon precursor gas such as SiCl4 and H2 is introduced to grow the Si within the trench and form a seamless silicon whisker. Optionally, an etch or a chemical mechanical polish (CMP) step is applied to lower the Si growth to a level that is coplanar with the top of the trench.
In a second embodiment, a layer of silicon is deposited by chemical vapor deposition (CVD) on the sidewalls of a via hole or trench and then a seed material such as Ni, Ti, or Co or an alloy of one of these metals is deposited on the silicon layer by electroless plating. The seed material and the silicon layer are each from 500 to 1000 Angstroms thick and are reflowed by a heat treatment to provide a liquid comprised of a silicide that has a metal silicon ratio slightly larger than 1. The silicide fills most of the via hole or trench. Then a silicon precursor gas such as SiCl4 and H2 is applied to adjust the metal/silicon ratio to a targeted value and grow the silicide to form a seamless silicide layer. Optionally, an etch or CMP step is used to lower the overgrown silicide to a level that is coplanar with the top of the opening.